SIWave parallel plate capacitor simulation
Dracarys99
Member
in Electronics
Reading on the internet, I see that it is possible to simulate a PCB modelling it as a large parallel plate capacitor and obtain the Impedance vs Frequency plots, where we can see the "spikes" towards the left side of the graph, something like this:-
How can I simulate this on SIwave? I tried the following:-
To have only 2 metal layers separated by a dielectric layer (setting this up using Layer Stack up editor) and then added a voltage source using the circuits components option in SIwave 17.2. But this seems to be wrong, and I obviously do not have any nets etc or a GND plane for that matter, so that I can have a potential difference between the plates.
Please suggest a method to obtain this simulation.
Thank you.
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Answers
Hi Dracarys99,
Instead of SIwave, Q3D Extractor is an appropriate choice for parallel plate capacitor simulation. Ansys Q3D Extractor can extract RLCG parameters after performing 2D and 3D quasi-static electromagnetic field simulations. Good luck!
Best,
Manny.
Hi @manny
I tried HFSS and Q3D. In both cases, I made a 50mmx50mm parallel plate capacitor with 2mm of FR4 dielectric in between. I get the capacitance value correct, but I think I have to use the DrivenModal solution type in HFSS for getting the impedance vs freqeuncy plot like I mentioned above. Also, I can't get how to assign (and where) a lumped port, I think I have to use this as well.
It will helpful if you outline the process of getting the graph I need (as I mentioned above) in Q3D (or in HFSS).
Thank you.
I want to get a result like this @manny
@EM2020 @rtk
For this problem I am getting the correct capacitance but the impedance vs frequency graph that I plot has an exponentially decaying to zero curve, nothing like the graph I need (posted above). What am I doing wrong? @manny @nchode @AndyJP