am using 30 passes but it shoots error even before reaching to the number I set. Also, as it looks very unstable, I am setting "minimum converged passes" to 2 rather than 1.

It did not help.

I hope this schematic helps. I am designing a CPW line in a super thin substrate wafer (quartz). so T_Quartz is set around 10-20um. Accordingly, W and G must be set super small (sub-um) to meet our design goals.
This is a screen capture from HFSS 2022R1.
the yellow areas are all PEC boundaries as the thickness of conductors is very small too.

It does not shoot error when "W" in the previous screen capture was large like more than 100um. However, we have to design a very narrow line for our applications.
In the HFSS design screen capture the block at the center in the top screen capture was not included.

Yes will do. but when I increased W and G, the problem never happens. I seems like due to very small mesh size required to simulate.
Any material useful for this problem?