I am seeing the same error in Siwave, even though I belive there is no error in the stackup. I have imported the same design into Electronics Workbench, and there I am not seeing an error. There are two layers out of 6 where the VSS fill is > 90%, so they should automatically be detected as planes. VSS is identified as a power/ground net.
In addition, for some types of simulations (SYZ) I get the following error:
Metal layer "L05" is sitting in an air bubble; please change surrounding dielectric material using the Layer Stack Editor
I have tried evrything I can think of to resolve this, no edit I make to the stackup has any effect. The surrounding layers are defined exactly as the other dielectric layers in the design, and I am not getting errors for those layers.
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