August 17, 2023 at 10:26 pm
Guanhui Wang
Ansys Employee

Hi Hannah Nguyen,

Thank you for the post. For the questions:

  1. About the delay element, I suspect it's because of the INTERCONNECT sample mode simulation method. When the circuit is turned on, all elements start to work. In time domain the signal transfers from one element to another, and the elements wait for the signal will pad 0s at all the ports. Could you please share with us your file for further investigate on this?
  2. I don't think you can resolve such a thin linewidth with a short simulation time. What do you want to measure and maybe we can find some other analytical ways to do this.