March 8, 2023 at 1:38 pmwaqar muhammadSubscriber
Hi. I am doing a simple chip level iterconnect simulation and there are three variations of the simulation, Namely single conductor, multiple conudctors and multiple conductors with solve inside. First single conductor simulation works fine as shown in figure 1. Second simulation works but the results do not match with the first simulation. Whereas, the thrid simulation gives error. Can anybody help me in understanding why the results do not match and why third simulation gives error. I have attached the simulation files.https://drive.google.com/file/d/16RpsO4G_g3HuiHrghEReL_h67xmmDFt3/view?usp=sharing
Simulation 1: single conductor with top and bottom ground plane. This simulation gives correct result
Simulation 2: single conductow with right, left, top and bottom ground. Right and left ground do not have solve inside set. This simulation gives incorrect result
Simulaton 3: single conductor with right, left, top and bottom ground. Right and left ground have solve inside set. This simulation gives error
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