Designing circuit structures using full-wave optimization and lumped BCs

    • holloway



      I'm designing a binary traveling wave phase modulator on an integrated circuit process using HFSS and ADS. Active devices are used as switches. Nominal impedances for these devices at a given bias point were obtained via circuit models. This nominal impedance (in the "switch on" and "switch off" states were used to tune a full-wave model by using lumpedRLC boundary conditions. The model was driven with two lumped ports (a slot line input and microstrip output). The HFSS-simulated results match physical expectations.

      The lumped RLC boundary conditions were then replaced (the same surface objects were utilized) with lumped ports. The resultant 4-port was simulated in HFSS and the S-Matrix was exported (normalized, of course, to 50 Ohm). This touchstone file was then utilized in a circuit simulation (ADS) to re-create the previously-simulated response by loading the two "new" ports with the same complex impedances previously used. The resultant 2-port response differs significantly from the original HFSS-only modeled response. 

      I've included a PDF with some of the details. In short, wave ports have been attempted on the input and output ports. Different characteristic impedances for the new "switch terminal ports" have been tried. The model has been split into two sections in an attempt to prevent any wave circulation in the 4-port structure. The fields around the new switching ports have been verified to be TEM in nature. 

      None of these changes have significantly changed the response I see in ADS. 

      Any thoughts would be greatly appreciated. 

    • ansysqueries

      Hi holloway, I have been facing a similar problem. There is a significant difference in the results when lumped RLCs are replaced by lumped ports and then the snp file is exported to ADS to recreate the same results. Have you found any solution to this problem? Any help will be appreciated. 

    • Peter Serano
      Ansys Employee

      @holloway - Your issues are coming up because you are defining a differential port in HFSS and then modeling it as a single-ended port with common ground reference in ADS. - Instead of using ADS, I would recommend using the built-in circuit simulator inside ANSYS Electronics Desktop. 

      Take a look at this post for instructions on how to setup a circuit model with differential ports in the AEDT Circuit Simulator: https://forum.ansys.com/forums/topic/lumped-rlcs-vs-lumped-ports-in-hfss-substantial-difference-in-the-results/

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