Electronics

Electronics

HFSS separation of simulation elements

    • Edoardo Pelliccia
      Subscriber

      hello,

      I have the need to simulate a chip which is composed by a top portion and a bottom portion, connected by four bumps at the edge of each corner. The top chip has a bunch of lumped ports which represents lumped capacitors (that we include by simulation in a circuital simulator), while the bottom chip has 2 ports at the bottom which are the input and output of the device. I wanted to try and separate the two chips with two different simulation which then are joined in an external circuital sim, but, until now, I was not able to achieve this since the results of the two simulations technique (two separate sims, one per chip, and one big simulations) do not yield the same results.

      do you have suggestions on techniques to use to overcome this issue?

    • Praneeth
      Ansys Employee

       

      Hi Edoardo Pelliccia,

      Please provide more details to help us serve you better.

      Kindly let us know which Ansys tool you want to use and what type of analysis you need to carry.

      For your upcoming posts, you can add tags to your posts on the learning forum which can help the forum community.

      Best regards,
      Praneeth.

       

    • Edoardo Pelliccia
      Subscriber

      Hi Praneeth,

      I'm using HFSS, and I need to carry out the analysis of the routing of a miniaturized chip, composed of two bumped chips, A and B. The chip A, at the top, is composed of some components, which are modeled externally with a vendor library, and the interconnects are modeled in HFSS. The chip B only contains metal interconnects.

      The two chips are connected with a bumping ball, and I wanted to use this feature to split the simulation, under the assumption that there is no EM effect between the two devices. So, in the place of the bumping ball for both chip A and chip B, I am drawing a vertical lumped port referred to a common PEC plate at the top, and then interconnecting twose two simulations in a circuital tool. Until now, this approach failed, since the result with the two separate chips is different from the result with the chips united. 

      I hope my explanation is clear enough.

      Kind regards,

      Edoardo

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