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Electronics

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Issues when running SIwizard for differential high-speed links

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    • Alexandre L
      Subscriber

      Hello,

      I am trying to run SIwizard to extract S-parameters of several high speed links between 2 ICs, and then use Ansys electronic desktop to get my eye diagrams. Few questions:

      1) When running SIwizard for a line between 2 ICs with a serial passive component (capacitor), the passive component breaks the net (left and right nets have different names). Is there a way for the SIwizard to "ignore" that capacitor and attach the 2 nets together? Or would you recommend running the simulation twice, first between IC1 and capacitor, and second between capacitor and IC2.

       

      2) After SIwizard is done with S-parameters computing, I am getting the following error on AEDT:

      This error makes me unable to get any result. Could you please tell me how to fix that error?

       

      Regards,

      Alexandre

       

       

    • Nathan B
      Ansys Employee

       

      1) You will need to create Extended nets or if you have differential nets you would need to create Extended Differential nets.  To create Extended nets select the nets on both sides of the capacitor, right click > Create Extended nets. If you need to create Extended Differential nets, then select two Extended nets, right click > Create Extended Differential Pair… You will now see the Extended Differential Pair listed in the SIwizard under the Extended DIfferential tab. 

       

    • Dan Dv
      Ansys Employee

      For the second item, that is a non-specific error that just tells us that the Circuit part of the project did not run to completion. To debug that further you will have to open the AEDT project that was created by the SIwizard and look at what messages were generated for the transient solve on that side. If you can post more info from that part here, I will hopefully be able to provide more specific details. 

    • Alexandre L
      Subscriber

      Hello,

      @Nathan Thank you for your answer, it worked for me.

       

      @Dan So I have tried some stuff to attempt correcting the errors, but did not succeed so far. This is the logs on aedt:

      I tried modifying my source to PRBS, but still get the "no valid bit sequence" error.

       

    • Dan Dv
      Ansys Employee

      Hello Alexandre ,

      That errors state that there are two eye source components on your schematic that don't have bit patterns set. Click on the proprities for those components, select hte "Bits" tab and the click on the box next to the "Bit Pattern" property to bring up the form to specify the bit patter for those sources. If you provide a valid setting in that form, it should get you past that error. Please let me know how it goes. 

      Best regards,

      -Dan

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