April 27, 2021 at 3:42 pmbsrSubscriberHi,
- What is the right approach for analyzing i.e. evaluating parasitics of the pcb design with Altium? I am using ODB++ files of Altium, importing in SiWave and then exporting using Q3D extractor?
- How do I ensure that the exported design for Q3D analysis has hollow vias? Under export options, this setting is unchecked "100% via fill (overrides per-padstack plating ratio)". Just to give more context, I can only choose top and bottom faces of the vias within Electromangnetic suite while assigning excitation. If hollow vias are available, then I might be able to choose the inner cylinder of the via. How can I validate whether a hollow or filled via is exported using Q3D extractor option?
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