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RAM optimization and source design mesh linking

    • vadisam
      Subscriber

      Hi,


      I am trying to simulate my full chip design which has a planar CPW transmission line structure along with an oscillator which is capacitively coupled to the transmission line. I am interested in the two port S parameter simulation (driven modal). The design requires fine meshing near the coupling site so that I can capture the oscillator's resonance frequency accurately. This results in a mesh size which typically requires about 7-8 million tetrahedrons. I also have certain mesh operations which achieves a minimum tetrahedron count which the adaptive meshing then build off on this initial seed mesh. 


      I first use a multi-frequency solution setup to accurately get the S parameters (based on the convergence) at a few frequencies where I expect the oscillator's resonance frequency is. This itself takes about a 1-1.5 days of simulation time. I then use this as a source design (source mesh) which I then import to a target design where I would like to use this solution to do a parametric sweep. I am only changing the inductance of the oscillator. 


      Here are my questions:


      1. I am using Ansys Electronics desktop 2019 on a 20 core machine with 512 GB RAM with HPC option. The CPU usage indicates that HFSS is only utilizing less than 10% of the RAM for doing the adaptive meshing for different passes. Can this be optimized so I can run the simulation faster? 


      2. When I link the source mesh from one design to a new target design which aims at doing the optimetrics sweep for inductance with the same geometry as the source design, why does HFSS require me to solve the source solution again? Why doesn't it use the source design solution to do the optimetrics?


      Thanks!

    • dprestau
      Ansys Employee

      Hi,


      I am trying to simulate my full chip design which has a planar CPW transmission line structure along with an oscillator which is capacitively coupled to the transmission line. I am interested in the two port S parameter simulation (driven modal). The design requires fine meshing near the coupling site so that I can capture the oscillator's resonance frequency accurately. This results in a mesh size which typically requires about 7-8 million tetrahedrons. I also have certain mesh operations which achieves a minimum tetrahedron count which the adaptive meshing then build off on this initial seed mesh. 


      I first use a multi-frequency solution setup to accurately get the S parameters (based on the convergence) at a few frequencies where I expect the oscillator's resonance frequency is. This itself takes about a 1-1.5 days of simulation time. I then use this as a source design (source mesh) which I then import to a target design where I would like to use this solution to do a parametric sweep. I am only changing the inductance of the oscillator. 


      Here are my questions:


      1. I am using Ansys Electronics desktop 2019 on a 20 core machine with 512 GB RAM with HPC option. The CPU usage indicates that HFSS is only utilizing less than 10% of the RAM for doing the adaptive meshing for different passes. Can this be optimized so I can run the simulation faster? 


      2. When I link the source mesh from one design to a new target design which aims at doing the optimetrics sweep for inductance with the same geometry as the source design, why does HFSS require me to solve the source solution again? Why doesn't it use the source design solution to do the optimetrics?


      Thanks!


      Hello,


      I will comment: HFSS will naturally uses hardware ressources as effectively as it and you can 't do much about it but you can do much more at the input file for the simulation to increase effectiveness.


      - first thing to check is if you can this model with HFSS3D layout because it is the most robust way to handle very large design. It handles better complex geometry and some simplification are more easily done here.


      - For instance, you can try to make equivalent substrate when dealing with many very small layers..actually you can go to the HFSS solver set up tab and ask in the modeling option if you want to merge substrate thinner than specific value or make 2D metal from thick conductor.


      - another possibility is to minimize the number of segments for the vias so that you can make them with few segments . 


      These two modeling change will have a big impact on initial number of tets...and from that HFSS should do the job without much help.


      On the solver side, you should also choose "mixed order" because you have many electrically small details. You may also choose iterative solver (and residual bigger than default..I choose 1e-4 usually ..) if ram is an issue...


      For CPU usage, you need to specify in the HPC settings the number of cores you want to use...specify the number of physical cores..you should see in most case, the cores are used well even though some process ( remeshing currently for instance) are single core but you can't do anything on it.


       


      On 2, I wonder if you checked to save the field in the optimetrics last tab...  


    • vadisam
      Subscriber

      Hi dprestau,


      Thanks for getting back. Here's my followup. Hope you can take the time out to answer them.


      - first thing to check is if you can this model with HFSS3D layout because it is the most robust way to handle very large design. It handles better complex geometry and some simplification are more easily done here.


      I am using the basic HFSS module, not HFSS3D. In my case, the substrate is 530um Si with all conducting layers set as 2D sheets (perfect electrical conductors). Do you think using HFSS3D in this case has an advantage?  


      - For instance, you can try to make equivalent substrate when dealing with many very small layers..actually you can go to the HFSS solver set up tab and ask in the modeling option if you want to merge substrate thinner than specific value or make 2D metal from thick conductor.


      I use 530um Si substrate thickness. My understanding is that for the CPW to be 50 ohm, it depends on the width, gap of the geometry along with the height of the substrate. So I use the thickness as is. 


      - another possibility is to minimize the number of segments for the vias so that you can make them with few segments 


      I dont have any vias. 


      On the solver side, you should also choose "mixed order" because you have many electrically small details. You may also choose iterative solver (and residual bigger than default..I choose 1e-4 usually ..) if ram is an issue...


      I use mixed order with iterative solver with the residual set to default, 1e-6


      For CPU usage, you need to specify in the HPC settings the number of cores you want to use...specify the number of physical cores..you should see in most case, the cores are used well even though some process ( remeshing currently for instance) are single core but you can't do anything on it.


      I actually specify the total number of logical processors. In my case, i use a 20 core machine with 40 logical cores. So i specify 40 in the HPC settings.


      On 2, I wonder if you checked to save the field in the optimetrics last tab...  


      Yes, the save fields and mesh checkbox is ticked. Is this why my optometrics variations take so long?


      Thanks!

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