Photonics – Chinese

Photonics – Chinese

run Verilog-A PAM4 Transceiver example report errors

    • ceshi xiazai

      Dear Lumerical Support team,

      When I downloaded the  example ‘Verilog-A PAM4 Transceiver’ from Verilog-A PAM4 Transceiver - Cadence Interoperability – Ansys Optics,  errors were reported after running it in Cadence Virtuoso, I followed the tutorial at the link step by step and did not make any changes, errors were as follows:


      ERROR (WIA-1175): Cannot plot waveform signals because no waveform data is available for plotting.
      One of the possible reasons can be that 'Save' check box for these signals are not selected in the Outputs Setup pane. Ensure that these check boxes are selected before you run the simulation.
      ERROR (EXPLORER-5031): While simulating run ExplorerRun.0, point 1, test Sim:INV_VTH:1, received error:
      Simulation Error:
      Simulator failed to complete the simulation.
      The simulator process returned a non-zero exit code, indicating failure.
      The simulator could have crashed or intentionally returned to indicate an error.
      Check the simulator log file for more information.  Common causes:
      1. Simulator may have crashed during exit even after reporting success in log file.
      2. Abrupt automatic simulator termination (e.g., SIGKILL) because the simulator process has
         exceeded resource limits, which can be specified in the distribution system or
         by the kernel itself (e.g., the Linux OOMKiller).
      3. Manual termination of the simulator process.
      ./runSimulation can be manually run in this directory to check the issue.


      Do you know any possible reasons for the errors reported?

      My software version:

      Cadence Virtuoso ICADVM18.1;



      The 'save' check box mentioned in ERROR1175, the screenshot of the example in the above link is selected, but when I run it, it is grayed out and cannot be selected;
      As for ERROR5031, I'm not sure what the reason is?


    • fengyang han


      • ceshi xiazai


    • Kyle
      Ansys Employee

      Hello, I believe your version of Virtuoso is too old. Please double check that your system meets the requirements on System Requirements and Environment Settings for Verilog-A CMLs – Ansys Optics:

      • ceshi xiazai


        Thank you for your reply。my virtuoso version is icadvm20.1-64b.500.24. Is this feasible? Are you aware of any other possible reasons?

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