November 12, 2020 at 6:58 pmDracarys99Subscriber
Reading on the internet, I see that it is possible to simulate a PCB modelling it as a large parallel plate capacitor and obtain the Impedance vs Frequency plots, where we can see the "spikes" towards the left side of the graph, something like this:-November 13, 2020 at 2:49 pmmannyAnsys EmployeeHi Dracarys99,nInstead of SIwave, Q3D Extractor is an appropriate choice for parallel plate capacitor simulation. Ansys Q3D Extractor can extract RLCG parameters after performing 2D and 3D quasi-static electromagnetic field simulations. Good luck!nBest,nManny.nNovember 16, 2020 at 9:04 amDracarys99SubscribernI tried HFSS and Q3D. In both cases, I made a 50mmx50mm parallel plate capacitor with 2mm of FR4 dielectric in between. I get the capacitance value correct, but I think I have to use the DrivenModal solution type in HFSS for getting the impedance vs freqeuncy plot like I mentioned above. Also, I can't get how to assign (and where) a lumped port, I think I have to use this as well. nIt will helpful if you outline the process of getting the graph I need (as I mentioned above) in Q3D (or in HFSS).nThank you.nNovember 16, 2020 at 3:29 pmNovember 19, 2020 at 10:47 amDracarys99SubscribernDecember 25, 2020 at 6:08 amDracarys99SubscriberFor this problem I am getting the correct capacitance but the impedance vs frequency graph that I plot has an exponentially decaying to zero curve, nothing like the graph I need (posted above). What am I doing wrong?nViewing 5 reply threads
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