November 12, 2020 at 6:51 pmDracarys99Subscriber
I am trying to do the resonant mode analysis for my PCB which is a ZCS Buck converter. It is a 2 layer PCB, but in the layer stack up editor of SIWave I see that the last layer always shows elevation = 0mm, regardless of any PCB that's been imported. I am getting this error while trying to find the voltage difference between top and bottom layerNovember 13, 2020 at 2:34 pmmannyAnsys EmployeeHi Dracarys99,nA similar question came up on another thread where I had mentioned that your 2-layer PCB should have both a power and a ground plane. In SIwave, for resonances to occur, there must be at least one pair of planes (power or ground) overlapping one another to form a resonant cavity. If there is no such pair, SIwave will generate this error could not locate requested layer pair. Also, printed circuit boards with only two layers are prone to this issue. This is because of the limited number of metal layers, which makes it hard to dedicate supply planes. In such boards, power and ground are often routed with traces instead of planes. nIn sum, plane-pair requirement for resonant mode simulations in SIwave is critical. nGood luck with your simulation. nBest,nMannynNovember 13, 2020 at 5:30 pmDracarys99SubscriberHello Manny,nYes, I'd asked this question on a different thread, but as its title was far field simulation I thought of asking as a separate question. nOn my board, I do have a GND plane, but not a power plane. Now that you said it explicitly, I have understood what you meant. So there is no way to do this resonant mode calculation for a 2 layer PCB? Do you have any suggestions as to what I could do for simulating this on this board?.Thank you,nRegards,nDracarys99nNovember 16, 2020 at 3:15 pmDracarys99SubscribernI haven't yet found any solution to analyze this for a 2- layer PCB, I think that this concept is not applicable to a 2-layer board according to your earlier explanation.nHere I have tried this for a 4-layer PCB, which still gives a similar error when one of the layers I select is top layer.nIt does not seem to work correctly even for the other layers I can't figure out why. The mesh looks like this:-nFor this board there is a gate driver IC which has an isolation barrier. When I try to run DC-IR simulation only the left half of the board is being taken into account. How do I make sure the whole board is included? I think I am going wrong in the assignment of pin groups or the current sources.nnPlease help.Thank you.nViewing 3 reply threads
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