December 26, 2022 at 2:24 pmFrederic WuSubscriber
I want to know if this is a glitch in simulation or a design problem because I cannot think of a physics principle related to this phenomenon.
The red blocks are silicon and the purple blocks are silicon oxide
A DBR targeting 2.5 µm is provided below
DBR targeting 2.5 µm
The problem I am facing currently is that when I add additional layers targeting 2.8µm below the original DBR that is targeting 2.5µm, there is a sudden drop in reflected power at around 3µm. Given that there are little transmission from the 2.5µm and that there are no cross-wavelength interference when using a DFT monitor, why is the reflected power affected when I add additional layers below the original DBR that targets 2.5µm? You can compare the above graphs with the graphs below. Please help me out, thanks.
Stacked DBR with layers targeting 2.5µm above layers targeting 2.8µm:
December 27, 2022 at 7:29 pmGuilin SunAnsys Employee
I believe this is how the DBR works. With certain thickness, it selects a wavelength to reflect. It is physical.
If the desired wavelength is not exactly what you want, you may need to optimize it,
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